| Parameter | Description |
|---|---|
| IF channels | |
| Center frequency1) (MHz) | 50 |
| Bandwidth2) (MHz) | 9 |
| Full-scale sensitivity3) (dBm) | 11 |
| ADCs | |
| Channels | 4 |
| Resolution | 14 |
| Speed (MSPS) | 125 |
| DACs | |
| Channels | 2 |
| Resolution | 14 |
| Update rate (MSPS) | 260 |
| Clocks | |
| Clock management | Using AD9512 |
| Maximum external clock (GHz) | 1.6 |
| Clock dividers | independent for ADC and DAC |
| Divide ratios | 1–32 |
| Phase adjustment | DAC clock |
| General | |
| FPGA | XC3S1000-4FT256 |
| Host interface | High-speed USB 2.0 |
| Expansion connector | 8 LVDS differential pairs |
| Analog monitoring | FPGA core supply current, LO rms, +5V, 2 analog output loopbacks |
| Low-speed DAC | |
| Channels | 12 |
| Resolution | 12 |
| Maximum update rate (kSPS) | 520 |
| Low-speed ADC | |
| Channels | 2 |
| Resolution | 12 |
| Maximum sampling rate (kSPS) | 50 |