EPICS Interface to LLRF4

EPICS Interface to LLRF4

LLRF4+EPICS EPICS interface to LLRF4 evaluation board is currently being developed at Dimtel, Inc. The board is pictured here with a Linux development machine running both the softIOC and the user interface (via EDM). A special development version of the FPGA gateware produces 96 MHz signal which is used to clock the signal processing chain. One of the two DAC outputs is routed to an ADC and is used as an arbitrary waveform generator for developing, testing, and demonstrating functional signal processing features.

news/archive/20081125.txt · Last modified: 2014/06/03 23:17 by dimtel
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