Terminating the IOC

System information:
  Function:        feedback
  Harmonic number: 176
  Demultiplexing:  UES
  Revision:        3.13
  Serial number:   IGP12_0067

           STARTING THE AUTOMATED TEST SEQUENCE

Testing internal blockRAM:                                  [OK]
Testing external SRAM: USB:                                 [OK]
Testing general-purpose digital inputs/outputs:             [OK]
Verifying RF clock presence and DCM lock:                   [OK]

Testing low-speed DAC/ADC system
Ch(ADC)	ADC(mV)	DAC(mV)	Off(mV)	DAC(mV)	ADC(mV)
0	-2048	-2068	   -2	 2071	 2046
1	-2048	-2071	    6	 2059	 2047
2	-2048	-2078	   10	 2057	 2046
3	-2048	-2065	   -3	 2072	 2047
4	-2048	-2074	    0	 2072	 2047
5	-2047	-2055	  -12	 2081	 2047
6	-2047	-2063	   -6	 2074	 2047
7	-2048	-2064	   -7	 2077	 2046

Testing high-speed DAC offset channel
Offset DAC(cnt)	Fast ADC(cnt)
-8192		-183.8
-244		  0.1
8191		198.1

Testing high-speed DAC output
HS DAC(cnt)	HS ADC(cnt)
-2048		-1069.3
   -1		   0.0
 2047		1073.5

Environmental measurements
Bulk supply voltage (12V):                                  11.96
Vcc supply voltage (3.3V):                                   3.30
FPGA core supply voltage (1.0V):                             1.00
Analog 5V supply voltage (5.0V):                             5.00
Analog 3.3V supply voltage (3.3V):                           3.30
iGp board temperature (deg C):                              26.2
FPGA temperature rise (deg C):                              -0.3
ADC clock delay temperature rise (deg C):                    4.1
DAC clock delay temperature rise (deg C):                    3.2
