Terminating the IOC

System information:
  Function:        feedback
  Harmonic number: 372
  Demultiplexing:  UES
  Revision:        4.09
  Serial number:   IGP12_0124

           STARTING THE AUTOMATED TEST SEQUENCE

Testing internal blockRAM:                                  [OK]
Testing external SRAM: USB:                                 [OK]
Testing general-purpose digital inputs/outputs:             [OK]
Verifying RF clock presence and DCM lock:                   [OK]

Testing low-speed DAC/ADC system
Ch(ADC)	ADC(mV)	DAC(mV)	Off(mV)	DAC(mV)	ADC(mV)
0	-2048	-2072	    0	 2071	 2047
1	-2048	-2062	   -2	 2065	 2047
2	-2048	-2071	    6	 2057	 2047
3	-2048	-2057	  -12	 2080	 2047
4	-2048	-2076	    6	 2063	 2047
5	-2048	-2065	   -2	 2067	 2047
6	-2048	-2076	   11	 2051	 2047
7	-2048	-2055	  -18	 2079	 2047

Testing high-speed DAC offset channel
Offset DAC(cnt)	Fast ADC(cnt)
-8192		-216.4
 868		  0.0
8191		175.5

Testing high-speed DAC output
HS DAC(cnt)	HS ADC(cnt)
-2048		-1093.7
    0		  -0.1
 2047		1094.0

Environmental measurements
Bulk supply voltage (12V):                                  11.80
Vcc supply voltage (3.3V):                                   3.30
FPGA core supply voltage (1.0V):                             1.00
Analog 5V supply voltage (5.0V):                             5.02
Analog 3.3V supply voltage (3.3V):                           3.30
iGp board temperature (deg C):                              25.4
FPGA temperature rise (deg C):                               0.7
ADC clock delay temperature rise (deg C):                    6.5
DAC clock delay temperature rise (deg C):                    5.8
