Terminating the IOC

System information:
  Function:        feedback
  Harmonic number: 184
  Demultiplexing:  UES
  Revision:        3.08
  Serial number:   IGP12_0055

           STARTING THE AUTOMATED TEST SEQUENCE

Testing internal blockRAM:                                  [OK]
Testing external SRAM: USB:                                 [OK]
Testing general-purpose digital inputs/outputs:             [OK]
Verifying RF clock presence and DCM lock:                   [OK]

Testing low-speed DAC/ADC system
Ch(ADC)	ADC(mV)	DAC(mV)	Off(mV)	DAC(mV)	ADC(mV)
0	-2048	-2064	   -8	 2080	 2047
1	-2048	-2064	    0	 2065	 2047
2	-2048	-2073	    9	 2056	 2047
3	-2048	-2067	    1	 2065	 2047
4	-2048	-2067	   -3	 2074	 2047
5	-2048	-2063	   -3	 2068	 2047
6	-2048	-2083	   19	 2044	 2046
7	-2048	-2068	    0	 2067	 2046

Testing high-speed DAC offset channel
Offset DAC(cnt)	Fast ADC(cnt)
-8192		-199.4
 291		 -0.5
8191		186.7

Testing high-speed DAC output
HS DAC(cnt)	HS ADC(cnt)
-2048		-1083.2
   -2		   0.1
 2047		1083.8

Environmental measurements
Bulk supply voltage (12V):                                  11.99
Vcc supply voltage (3.3V):                                   3.30
FPGA core supply voltage (1.0V):                             1.00
Analog 5V supply voltage (5.0V):                             5.00
Analog 3.3V supply voltage (3.3V):                           3.30
iGp board temperature (deg C):                              27.6
FPGA temperature rise (deg C):                               1.8
ADC clock delay temperature rise (deg C):                    3.5
DAC clock delay temperature rise (deg C):                    5.0
