llrf Project Status (11/12/2012 - 03:52:56)
Project File: llrf.xise Parser Errors: No Errors
Module Name: llrf Implementation State: Programming File Generated
Target Device: xc3s1000-5ft256
  • Errors:
No Errors
Product Version:ISE 14.2
  • Warnings:
6288 Warnings (4703 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
X 1 Failing Constraint
Environment: System Settings
  • Final Timing Score:
2450  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 4,708 15,360 30%  
Number of 4 input LUTs 5,015 15,360 32%  
Number of occupied Slices 3,588 7,680 46%  
    Number of Slices containing only related logic 3,588 3,588 100%  
    Number of Slices containing unrelated logic 0 3,588 0%  
Total Number of 4 input LUTs 5,257 15,360 34%  
    Number used as logic 4,926      
    Number used as a route-thru 242      
    Number used as 16x1 RAMs 14      
    Number used for Dual Port RAMs 24      
    Number used as Shift registers 51      
Number of bonded IOBs 157 173 90%  
    IOB Flip Flops 184      
Number of RAMB16s 18 24 75%  
Number of MULT18X18s 23 24 95%  
Number of BUFGMUXs 4 8 50%  
Number of DCMs 2 4 50%  
Average Fanout of Non-Clock Nets 2.53      
 
Performance Summary [-]
Final Timing Score: 2450 (Setup: 2450, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 1 Failing Constraint    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Nov 12 03:48:22 201201564 Warnings (0 new)47 Infos (1 new)
Translation ReportCurrentMon Nov 12 03:48:29 201204 Warnings (0 new)3 Infos (0 new)
Map ReportCurrentMon Nov 12 03:49:44 201204703 Warnings (4701 new)6 Infos (0 new)
Place and Route ReportCurrentMon Nov 12 03:52:29 201209 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportCurrentMon Nov 12 03:52:37 201206 Warnings (2 new)5 Infos (0 new)
Bitgen ReportCurrentMon Nov 12 03:52:54 201202 Warnings (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
Physical Synthesis ReportCurrentMon Nov 12 03:49:44 2012
WebTalk ReportCurrentMon Nov 12 03:52:55 2012
WebTalk Log FileCurrentMon Nov 12 03:52:56 2012

Date Generated: 11/12/2012 - 03:52:56