Project Statistics |
PROPEXT_SynthMultStyle_virtex2=Block |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthOptEffort=High |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2012-11-10T23:16:05 |
PROP_intWbtProjectID=07482C70AD8BC6B64237A3D6743223A9 |
PROP_intWbtProjectIteration=12 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_xilxBitgStart_IntDone=true |
PROP_xilxMapAllowLogicOpt=true |
PROP_xilxMapCoverMode=Speed |
PROP_xilxMapPackRegInto=For Inputs and Outputs |
PROP_xilxMapTimingDrivenPacking=true |
PROP_xilxPARplacerEffortLevel=High |
PROP_xilxPARrouterEffortLevel=High |
PROP_xilxPostTrceRpt=Error Report |
PROP_xilxSynthRegBalancing=Yes |
PROP_xstBusDelimiter={} |
PROP_xstEquivRegRemoval=false |
PROP_xstOptimizeInsPrimtives=true |
PROP_xstPackIORegister=Yes |
PROP_AutoTop=true |
PROP_DevFamily=Spartan3 |
PROP_MapLogicOptimization=true |
PROP_MapRegDuplication=On |
PROP_SynthMuxStyle=MUXCY |
PROP_DevDevice=xc3s1000 |
PROP_DevFamilyPMName=spartan3 |
PROP_MapExtraEffort=Normal |
PROP_xilxPARextraEffortLevel=Normal |
PROP_DevPackage=ft256 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-5 |
PROP_PreferredLanguage=Verilog |
FILE_UCF=1 |
FILE_VERILOG=28 |