Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.2 (ISE) - P.28xd Target Family: Spartan3
OS Platform: LIN64 Target Device: xc3s1000
Project ID (random number) dfe553b3fd134a1c892aa5e901532619.07482C70AD8BC6B64237A3D6743223A9.12 Target Package: ft256
Registration ID 175441000_177600169_209664023_225 Target Speed: -5
Date Generated 2012-11-12T03:52:55 Tool Flow ISE
 
User Environment
OS Name Fedora OS Release Fedora release 17 (Beefy Miracle)
CPU Name Intel(R) Core(TM) i7-2640M CPU @ 2.80GHz CPU Speed 1200.000 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Accumulators=11
  • 17-bit up accumulator=2
  • 27-bit up loadable accumulator=1
  • 43-bit up accumulator=8
Adders/Subtractors=154
  • 1-bit addsub=2
  • 10-bit addsub=2
  • 11-bit addsub=2
  • 12-bit addsub=2
  • 13-bit adder=4
  • 13-bit addsub=2
  • 14-bit addsub=2
  • 15-bit adder=1
  • 15-bit addsub=72
  • 15-bit subtractor=4
  • 16-bit subtractor=8
  • 17-bit adder=3
  • 18-bit adder=1
  • 2-bit addsub=2
  • 2-bit subtractor=1
  • 22-bit adder carry out=2
  • 28-bit subtractor=8
  • 3-bit addsub=2
  • 30-bit adder=1
  • 31-bit adder=2
  • 32-bit adder=1
  • 32-bit subtractor=1
  • 4-bit adder=1
  • 4-bit addsub=2
  • 43-bit subtractor=8
  • 5-bit addsub=2
  • 5-bit subtractor=1
  • 6-bit adder=2
  • 6-bit adder carry out=2
  • 6-bit addsub=2
  • 7-bit addsub=2
  • 7-bit subtractor=1
  • 8-bit addsub=2
  • 9-bit addsub=3
  • 9-bit subtractor=1
Comparators=3
  • 9-bit comparator equal=1
  • 9-bit comparator greater=1
  • 9-bit comparator not equal=1
Counters=14
  • 10-bit up counter=1
  • 12-bit up counter=3
  • 14-bit up counter=1
  • 16-bit up counter=1
  • 2-bit up counter=1
  • 25-bit up counter=1
  • 26-bit up counter=1
  • 3-bit up counter=1
  • 4-bit up counter=2
  • 6-bit down counter=1
  • 8-bit up counter=1
FSMs=3 Multiplexers=59
  • 1-bit 4-to-1 multiplexer=56
  • 14-bit 4-to-1 multiplexer=1
  • 32-bit 4-to-1 multiplexer=1
  • 32-bit 8-to-1 multiplexer=1
Multipliers=23
  • 15x14-bit registered multiplier=16
  • 16x14-bit registered multiplier=5
  • 16x16-bit registered multiplier=2
RAMs=3
  • 1024x32-bit dual-port block RAM=1
  • 12x14-bit single-port distributed RAM=1
  • 8x12-bit dual-port distributed RAM=1
Registers=4584
  • Flip-Flops=4584
Xors=6
  • 1-bit xor2=6
MiscellaneousStatistics
  • AGG_BONDED_IO=157
  • AGG_IO=157
  • AGG_SLICE=3588
  • NUM_4_INPUT_LUT=5257
  • NUM_BONDED_IOB=157
  • NUM_BUFGMUX=4
  • NUM_CYMUX=2640
  • NUM_DCM=2
  • NUM_DP_RAM=24
  • NUM_IOB_FF=184
  • NUM_LUT_RT=242
  • NUM_MULT18X18=23
  • NUM_RAM16=14
  • NUM_RAMB16=18
  • NUM_SHIFT=51
  • NUM_SLICEL=3518
  • NUM_SLICEM=70
  • NUM_SLICE_FF=4708
  • NUM_XOR=2633
NetStatistics
  • NumNets_Active=8691
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=424
  • NumNodesOfType_Active_BRAMDUMMY=988
  • NumNodesOfType_Active_CLKPIN=3235
  • NumNodesOfType_Active_CNTRLPIN=2010
  • NumNodesOfType_Active_DOUBLE=16616
  • NumNodesOfType_Active_DUMMY=14705
  • NumNodesOfType_Active_DUMMYBANK=413
  • NumNodesOfType_Active_DUMMYESC=24
  • NumNodesOfType_Active_GLOBAL=476
  • NumNodesOfType_Active_HFULLHEX=394
  • NumNodesOfType_Active_HLONG=106
  • NumNodesOfType_Active_HUNIHEX=2378
  • NumNodesOfType_Active_INPUT=19060
  • NumNodesOfType_Active_IOBOUTPUT=102
  • NumNodesOfType_Active_OMUX=7763
  • NumNodesOfType_Active_OUTPUT=8433
  • NumNodesOfType_Active_PREBXBY=5439
  • NumNodesOfType_Active_VFULLHEX=776
  • NumNodesOfType_Active_VLONG=109
  • NumNodesOfType_Active_VUNIHEX=1532
  • NumNodesOfType_Gnd_BRAMDUMMY=4
  • NumNodesOfType_Gnd_CNTRLPIN=62
  • NumNodesOfType_Gnd_DOUBLE=87
  • NumNodesOfType_Gnd_DUMMY=226
  • NumNodesOfType_Gnd_DUMMYBANK=2
  • NumNodesOfType_Gnd_HFULLHEX=1
  • NumNodesOfType_Gnd_INPUT=274
  • NumNodesOfType_Gnd_OMUX=166
  • NumNodesOfType_Gnd_OUTPUT=104
  • NumNodesOfType_Gnd_PREBXBY=62
  • NumNodesOfType_Gnd_VFULLHEX=5
SiteStatistics
  • IOB-DIFFM=70
  • IOB-DIFFS=76
  • SLICEL-SLICEM=1777
SiteSummary
  • BUFGMUX=4
  • BUFGMUX_GCLKMUX=4
  • BUFGMUX_GCLK_BUFFER=4
  • DCM=2
  • DCM_DCM=2
  • IOB=157
  • IOB_IFF1=79
  • IOB_INBUF=87
  • IOB_OFF1=60
  • IOB_OFF2=28
  • IOB_OFFDDRBLACKBOX=28
  • IOB_OUTBUF=87
  • IOB_PAD=157
  • IOB_TFF1=17
  • MULT18X18=23
  • MULT18X18_BLACKBOX=23
  • RAMB16=18
  • RAMB16_RAMB16=18
  • RAMB16_RAMB16A=18
  • RAMB16_RAMB16B=18
  • SLICEL=3518
  • SLICEL_C1VDD=134
  • SLICEL_C2VDD=121
  • SLICEL_CYMUXF=1337
  • SLICEL_CYMUXG=1303
  • SLICEL_F=2630
  • SLICEL_F5MUX=231
  • SLICEL_F6MUX=32
  • SLICEL_FFX=2061
  • SLICEL_FFY=2592
  • SLICEL_G=2538
  • SLICEL_GNDF=162
  • SLICEL_GNDG=158
  • SLICEL_XORF=1362
  • SLICEL_XORG=1271
  • SLICEM=70
  • SLICEM_F=19
  • SLICEM_FFX=4
  • SLICEM_FFY=51
  • SLICEM_G=70
  • SLICEM_WSGEN=70
 
Configuration Data
BUFGMUX
  • S=[S_INV:4] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:4]
  • S=[S_INV:4] [S:0]
DCM
  • PSCLK=[PSCLK_INV:1] [PSCLK:1]
  • PSEN=[PSEN_INV:1] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:1]
  • RST=[RST:2] [RST_INV:0]
DCM_DCM
  • CLKDV_DIVIDE=[2:2]
  • CLKOUT_PHASE_SHIFT=[FIXED:1] [VARIABLE:1]
  • CLK_FEEDBACK=[1X:2]
  • DESKEW_ADJUST=[8:2]
  • DFS_FREQUENCY_MODE=[LOW:2]
  • DLL_FREQUENCY_MODE=[LOW:2]
  • DUTY_CYCLE_CORRECTION=[TRUE:2]
  • FACTORY_JF1=[0XC0:2]
  • FACTORY_JF2=[0X80:2]
  • PSCLK=[PSCLK_INV:1] [PSCLK:1]
  • PSEN=[PSEN_INV:1] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:1]
  • RST=[RST:2] [RST_INV:0]
IOB
  • ICE=[ICE:17] [ICE_INV:0]
  • ICLK1=[ICLK1_INV:0] [ICLK1:79]
  • O1=[O1_INV:15] [O1:72]
  • O2=[O2:26] [O2_INV:2]
  • OCE=[OCE:18] [OCE_INV:1]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:61]
  • OTCLK2=[OTCLK2_INV:0] [OTCLK2:28]
  • SR=[SR:0] [SR_INV:56]
  • T1=[T1_INV:0] [T1:17]
  • TCE=[TCE_INV:0] [TCE:1]
IOB_IFF1
  • CE=[CE:17] [CE_INV:0]
  • CK=[CK:79] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:79]
  • IFF1_SR_ATTR=[SRLOW:52] [SRHIGH:4]
  • IFFATTRBOX=[SYNC:56]
  • LATCH_OR_FF=[FF:79]
  • SR=[SR:0] [SR_INV:56]
IOB_OFF1
  • CE=[CE:18] [CE_INV:1]
  • CK=[CK:60] [CK_INV:0]
  • D=[D:58] [D_INV:2]
  • LATCH_OR_FF=[FF:60]
  • OFF1_INIT_ATTR=[INIT0:55] [INIT1:5]
IOB_OFF2
  • CK=[CK:28] [CK_INV:0]
  • D=[D:26] [D_INV:2]
  • LATCH_OR_FF=[FF:28]
  • OFF2_INIT_ATTR=[INIT0:28]
IOB_OUTBUF
  • IN=[IN_INV:13] [IN:74]
  • TRI=[TRI_INV:0] [TRI:17]
IOB_PAD
  • DRIVEATTRBOX=[2:21] [4:4] [6:6] [8:32] [12:22] [24:2]
  • IOATTRBOX=[LVCMOS25:80] [LVCMOS33:77]
  • PULL=[PULLUP:4] [PULLDOWN:60]
  • SLEW=[SLOW:35] [FAST:52]
IOB_TFF1
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:17] [CK_INV:0]
  • D=[D:17] [D_INV:0]
  • LATCH_OR_FF=[FF:17]
  • TFF1_INIT_ATTR=[INIT0:17]
MULT18X18
  • CE=[CE:23] [CE_INV:0]
  • CLK=[CLK:23] [CLK_INV:0]
  • RST=[RST:23] [RST_INV:0]
MULT18X18_BLACKBOX
  • CE=[CE:23] [CE_INV:0]
  • CLK=[CLK:23] [CLK_INV:0]
  • RST=[RST:23] [RST_INV:0]
RAMB16
  • CLKA=[CLKA_INV:0] [CLKA:18]
  • CLKB=[CLKB_INV:0] [CLKB:18]
  • ENA=[ENA_INV:0] [ENA:18]
  • ENB=[ENB_INV:0] [ENB:18]
  • SSRA=[SSRA_INV:0] [SSRA:18]
  • SSRB=[SSRB_INV:0] [SSRB:18]
  • WEA=[WEA:2] [WEA_INV:16]
  • WEB=[WEB:18] [WEB_INV:0]
RAMB16_RAMB16A
  • CLKA=[CLKA_INV:0] [CLKA:18]
  • ENA=[ENA_INV:0] [ENA:18]
  • PORTA_ATTR=[1024X18:2] [4096X4:16]
  • SSRA=[SSRA_INV:0] [SSRA:18]
  • WEA=[WEA:2] [WEA_INV:16]
  • WRITEMODEA=[WRITE_FIRST:18]
RAMB16_RAMB16B
  • CLKB=[CLKB_INV:0] [CLKB:18]
  • ENB=[ENB_INV:0] [ENB:18]
  • PORTB_ATTR=[1024X18:2] [4096X4:16]
  • SSRB=[SSRB_INV:0] [SSRB:18]
  • WEB=[WEB:18] [WEB_INV:0]
  • WRITEMODEB=[WRITE_FIRST:18]
SLICEL
  • BX=[BX_INV:45] [BX:763]
  • BY=[BY:1184] [BY_INV:31]
  • CE=[CE:1254] [CE_INV:15]
  • CIN=[CIN_INV:0] [CIN:1300]
  • CLK=[CLK:2933] [CLK_INV:0]
  • SR=[SR:135] [SR_INV:0]
SLICEL_CYMUXF
  • 0=[0:1337] [0_INV:0]
  • 1=[1_INV:38] [1:1299]
SLICEL_CYMUXG
  • 0=[0:1303] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:231] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:32] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:614] [CE_INV:13]
  • CK=[CK:2061] [CK_INV:0]
  • D=[D:2054] [D_INV:7]
  • FFX_INIT_ATTR=[INIT0:2025] [INIT1:36]
  • FFX_SR_ATTR=[SRLOW:2052] [SRHIGH:9]
  • LATCH_OR_FF=[FF:2061]
  • REV=[REV_INV:0] [REV:3]
  • SR=[SR:81] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:1980] [SYNC:81]
SLICEL_FFY
  • CE=[CE:1134] [CE_INV:14]
  • CK=[CK:2592] [CK_INV:0]
  • D=[D:2561] [D_INV:31]
  • FFY_INIT_ATTR=[INIT0:2562] [INIT1:30]
  • FFY_SR_ATTR=[SRLOW:2559] [SRHIGH:33]
  • LATCH_OR_FF=[FF:2592]
  • SR=[SR:123] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:2469] [SYNC:123]
SLICEL_XORF
  • 1=[1_INV:36] [1:1326]
SLICEM
  • BX=[BX_INV:0] [BX:11]
  • BY=[BY:70] [BY_INV:0]
  • CLK=[CLK:70] [CLK_INV:0]
  • SR=[SR:70] [SR_INV:0]
SLICEM_F
  • DI=[DI:19] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:12]
  • LUT_OR_MEM=[RAM:19]
SLICEM_FFX
  • CK=[CK:4] [CK_INV:0]
  • D=[D:4] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:4]
  • FFX_SR_ATTR=[SRLOW:4]
  • LATCH_OR_FF=[FF:4]
  • SYNC_ATTR=[ASYNC:4]
SLICEM_FFY
  • CK=[CK:51] [CK_INV:0]
  • D=[D:51] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:51]
  • FFY_SR_ATTR=[SRLOW:51]
  • LATCH_OR_FF=[FF:51]
  • SYNC_ATTR=[ASYNC:51]
SLICEM_G
  • DI=[DI:70] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:12] [SHIFT_REG:51]
  • LUT_OR_MEM=[RAM:70]
SLICEM_WSGEN
  • CK=[CK:70] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:51]
  • WE=[WE_INV:0] [WE:70]
 
Pin Data
BUFGMUX
  • I0=4
  • O=4
  • S=4
BUFGMUX_GCLKMUX
  • I0=4
  • OUT=4
  • S=4
BUFGMUX_GCLK_BUFFER
  • IN=4
  • OUT=4
DCM
  • CLK0=2
  • CLK180=1
  • CLK2X=1
  • CLKFB=2
  • CLKIN=2
  • LOCKED=2
  • PSCLK=2
  • PSDONE=1
  • PSEN=2
  • PSINCDEC=2
  • RST=2
DCM_DCM
  • CLK0=2
  • CLK180=1
  • CLK2X=1
  • CLKFB=2
  • CLKIN=2
  • LOCKED=2
  • PSCLK=2
  • PSDONE=1
  • PSEN=2
  • PSINCDEC=2
  • RST=2
IOB
  • I=25
  • ICE=17
  • ICLK1=79
  • IQ1=79
  • O1=87
  • O2=28
  • OCE=19
  • OTCLK1=61
  • OTCLK2=28
  • PAD=157
  • SR=56
  • T1=17
  • TCE=1
IOB_IFF1
  • CE=17
  • CK=79
  • D=79
  • Q=79
  • SR=56
IOB_INBUF
  • IN=87
  • OUT=87
IOB_OFF1
  • CE=19
  • CK=60
  • D=60
  • Q=60
IOB_OFF2
  • CK=28
  • D=28
  • Q=28
IOB_OFFDDRBLACKBOX
  • OFF1=28
  • OFF2=28
  • OFFDDR=28
IOB_OUTBUF
  • IN=87
  • OUT=87
  • TRI=17
IOB_PAD
  • PAD=157
IOB_TFF1
  • CE=1
  • CK=17
  • D=17
  • Q=17
MULT18X18
  • A0=23
  • A1=23
  • A10=23
  • A11=23
  • A12=23
  • A13=23
  • A14=23
  • A15=23
  • A16=23
  • A17=23
  • A2=23
  • A3=23
  • A4=23
  • A5=23
  • A6=23
  • A7=23
  • A8=23
  • A9=23
  • B0=23
  • B1=23
  • B10=23
  • B11=23
  • B12=23
  • B13=23
  • B14=23
  • B15=23
  • B16=23
  • B17=23
  • B2=23
  • B3=23
  • B4=23
  • B5=23
  • B6=23
  • B7=23
  • B8=23
  • B9=23
  • CE=23
  • CLK=23
  • P0=5
  • P1=5
  • P10=5
  • P11=5
  • P12=5
  • P13=5
  • P14=22
  • P15=23
  • P16=23
  • P17=23
  • P18=23
  • P19=23
  • P2=5
  • P20=23
  • P21=23
  • P22=23
  • P23=23
  • P24=23
  • P25=23
  • P26=23
  • P27=23
  • P28=23
  • P29=4
  • P3=5
  • P30=2
  • P4=5
  • P5=5
  • P6=5
  • P7=5
  • P8=5
  • P9=5
  • RST=23
MULT18X18_BLACKBOX
  • A0=23
  • A1=23
  • A10=23
  • A11=23
  • A12=23
  • A13=23
  • A14=23
  • A15=23
  • A16=23
  • A17=23
  • A2=23
  • A3=23
  • A4=23
  • A5=23
  • A6=23
  • A7=23
  • A8=23
  • A9=23
  • B0=23
  • B1=23
  • B10=23
  • B11=23
  • B12=23
  • B13=23
  • B14=23
  • B15=23
  • B16=23
  • B17=23
  • B2=23
  • B3=23
  • B4=23
  • B5=23
  • B6=23
  • B7=23
  • B8=23
  • B9=23
  • CE=23
  • CLK=23
  • P0=5
  • P1=5
  • P10=5
  • P11=5
  • P12=5
  • P13=5
  • P14=22
  • P15=23
  • P16=23
  • P17=23
  • P18=23
  • P19=23
  • P2=5
  • P20=23
  • P21=23
  • P22=23
  • P23=23
  • P24=23
  • P25=23
  • P26=23
  • P27=23
  • P28=23
  • P29=4
  • P3=5
  • P30=2
  • P4=5
  • P5=5
  • P6=5
  • P7=5
  • P8=5
  • P9=5
  • RST=23
RAMB16
  • ADDRA10=18
  • ADDRA11=18
  • ADDRA12=18
  • ADDRA13=18
  • ADDRA2=16
  • ADDRA3=16
  • ADDRA4=18
  • ADDRA5=18
  • ADDRA6=18
  • ADDRA7=18
  • ADDRA8=18
  • ADDRA9=18
  • ADDRB10=18
  • ADDRB11=18
  • ADDRB12=18
  • ADDRB13=18
  • ADDRB2=16
  • ADDRB3=16
  • ADDRB4=18
  • ADDRB5=18
  • ADDRB6=18
  • ADDRB7=18
  • ADDRB8=18
  • ADDRB9=18
  • CLKA=18
  • CLKB=18
  • DIA0=18
  • DIA1=18
  • DIA10=2
  • DIA11=2
  • DIA12=2
  • DIA13=2
  • DIA14=2
  • DIA15=2
  • DIA2=18
  • DIA3=18
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIA8=2
  • DIA9=2
  • DIB0=16
  • DIB1=16
  • DIB2=16
  • DIB3=16
  • DIPA0=2
  • DIPA1=2
  • DOA0=18
  • DOA1=18
  • DOA10=2
  • DOA11=2
  • DOA12=2
  • DOA13=2
  • DOA14=1
  • DOA15=1
  • DOA2=18
  • DOA3=18
  • DOA4=2
  • DOA5=2
  • DOA6=2
  • DOA7=2
  • DOA8=2
  • DOA9=2
  • DOB0=2
  • DOB1=2
  • DOB10=2
  • DOB11=2
  • DOB12=1
  • DOB13=1
  • DOB2=2
  • DOB3=2
  • DOB4=2
  • DOB5=2
  • DOB6=2
  • DOB7=2
  • DOB8=2
  • DOB9=2
  • DOPA0=1
  • DOPA1=1
  • DOPB0=1
  • DOPB1=1
  • ENA=18
  • ENB=18
  • SSRA=18
  • SSRB=18
  • WEA=18
  • WEB=18
RAMB16_RAMB16
  • ADDRA=18
  • ADDRB=18
  • DIA=18
  • DIB=18
  • DOA=18
  • DOB=18
RAMB16_RAMB16A
  • ADDRA=18
  • ADDRA10=18
  • ADDRA11=18
  • ADDRA12=18
  • ADDRA13=18
  • ADDRA2=16
  • ADDRA3=16
  • ADDRA4=18
  • ADDRA5=18
  • ADDRA6=18
  • ADDRA7=18
  • ADDRA8=18
  • ADDRA9=18
  • CLKA=18
  • DIA=18
  • DIA0=18
  • DIA1=18
  • DIA10=2
  • DIA11=2
  • DIA12=2
  • DIA13=2
  • DIA14=2
  • DIA15=2
  • DIA2=18
  • DIA3=18
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIA8=2
  • DIA9=2
  • DIPA0=2
  • DIPA1=2
  • DOA=18
  • DOA0=18
  • DOA1=18
  • DOA10=2
  • DOA11=2
  • DOA12=2
  • DOA13=2
  • DOA14=1
  • DOA15=1
  • DOA2=18
  • DOA3=18
  • DOA4=2
  • DOA5=2
  • DOA6=2
  • DOA7=2
  • DOA8=2
  • DOA9=2
  • DOPA0=1
  • DOPA1=1
  • ENA=18
  • SSRA=18
  • WEA=18
RAMB16_RAMB16B
  • ADDRB=18
  • ADDRB10=18
  • ADDRB11=18
  • ADDRB12=18
  • ADDRB13=18
  • ADDRB2=16
  • ADDRB3=16
  • ADDRB4=18
  • ADDRB5=18
  • ADDRB6=18
  • ADDRB7=18
  • ADDRB8=18
  • ADDRB9=18
  • CLKB=18
  • DIB=18
  • DIB0=16
  • DIB1=16
  • DIB2=16
  • DIB3=16
  • DOB=18
  • DOB0=2
  • DOB1=2
  • DOB10=2
  • DOB11=2
  • DOB12=1
  • DOB13=1
  • DOB2=2
  • DOB3=2
  • DOB4=2
  • DOB5=2
  • DOB6=2
  • DOB7=2
  • DOB8=2
  • DOB9=2
  • DOPB0=1
  • DOPB1=1
  • ENB=18
  • SSRB=18
  • WEB=18
SLICEL
  • BX=808
  • BY=1215
  • CE=1269
  • CIN=1300
  • CLK=2933
  • COUT=1303
  • F1=2625
  • F2=2367
  • F3=1571
  • F4=765
  • F5=64
  • FXINA=32
  • FXINB=32
  • G1=2535
  • G2=2280
  • G3=1556
  • G4=750
  • SR=135
  • X=890
  • XB=2
  • XQ=2061
  • Y=882
  • YQ=2592
SLICEL_C1VDD
  • 1=134
SLICEL_C2VDD
  • 1=121
SLICEL_CYMUXF
  • 0=1337
  • 1=1337
  • OUT=1337
  • S0=1337
SLICEL_CYMUXG
  • 0=1303
  • 1=1303
  • OUT=1303
  • S0=1303
SLICEL_F
  • A1=2625
  • A2=2367
  • A3=1571
  • A4=765
  • D=2630
SLICEL_F5MUX
  • F=231
  • G=231
  • OUT=231
  • S0=231
SLICEL_F6MUX
  • 0=32
  • 1=32
  • OUT=32
  • S0=32
SLICEL_FAND
  • 0=52
  • 1=52
  • O=52
SLICEL_FFX
  • CE=627
  • CK=2061
  • D=2061
  • Q=2061
  • REV=3
  • SR=81
SLICEL_FFY
  • CE=1148
  • CK=2592
  • D=2592
  • Q=2592
  • SR=123
SLICEL_G
  • A1=2535
  • A2=2280
  • A3=1556
  • A4=750
  • D=2538
SLICEL_GAND
  • 0=44
  • 1=44
  • O=44
SLICEL_GNDF
  • 0=162
SLICEL_GNDG
  • 0=158
SLICEL_VDDG
  • 1=4
SLICEL_XORF
  • 0=1362
  • 1=1362
  • O=1362
SLICEL_XORG
  • 0=1271
  • 1=1271
  • O=1271
SLICEM
  • BX=11
  • BY=70
  • CLK=70
  • F1=19
  • F2=19
  • F3=19
  • F4=19
  • G1=70
  • G2=70
  • G3=70
  • G4=70
  • SR=70
  • X=19
  • XQ=4
  • Y=7
  • YQ=51
SLICEM_F
  • A1=19
  • A2=19
  • A3=19
  • A4=19
  • D=19
  • DI=19
  • WF1=19
  • WF2=19
  • WF3=19
  • WF4=19
  • WS=19
SLICEM_FFX
  • CK=4
  • D=4
  • Q=4
SLICEM_FFY
  • CK=51
  • D=51
  • Q=51
SLICEM_G
  • A1=70
  • A2=70
  • A3=70
  • A4=70
  • D=58
  • DI=70
  • WG1=19
  • WG2=19
  • WG3=19
  • WG4=19
  • WS=70
SLICEM_WSGEN
  • CK=70
  • WE=70
  • WSF=19
  • WSG=70
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-5 -timing -logic_opt off -ol high -t 1 -register_duplication on -cm speed -ir off -ignore_keep_hierarchy -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-5 -timing -logic_opt off -ol high -t 1 -register_duplication on -cm speed -ir off -ignore_keep_hierarchy -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-5 -cm speed -ir off -ignore_keep_hierarchy -pr b -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • map -intstyle ise -p xc3s1000-ft256-5 -timing -logic_opt off -ol high -t 1 -register_duplication on -cm speed -ir off -ignore_keep_hierarchy -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • trce -intstyle ise -e 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -e 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • map -intstyle ise -p xc3s1000-ft256-5 -timing -logic_opt on -ol high -xe n -t 1 -register_duplication on -cm speed -ir off -ignore_keep_hierarchy -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -e 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-5 -timing -logic_opt on -ol high -xe n -t 1 -register_duplication on -cm speed -ir off -ignore_keep_hierarchy -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -e 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-5 -timing -logic_opt on -ol high -xe n -t 1 -register_duplication on -cm speed -ir off -ignore_keep_hierarchy -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -e 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-5 -timing -logic_opt on -ol high -xe n -t 1 -register_duplication on -cm speed -ir off -ignore_keep_hierarchy -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -e 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-5 -timing -logic_opt on -ol high -xe n -t 1 -register_duplication on -cm speed -ir off -ignore_keep_hierarchy -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -e 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s1000-ft256-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1000-ft256-5 -timing -logic_opt on -ol high -xe n -t 1 -register_duplication on -cm speed -ir off -ignore_keep_hierarchy -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -pl high -rl high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -e 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 10 10 0 0 0 0 0
map 62 62 0 0 0 0 0
ngdbuild 55 55 0 0 0 0 0
par 63 63 0 0 0 0 0
trce 62 62 0 0 0 0 0
xst 34 34 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/dsm_c_design_summary_overview.htm ( 1 ) /doc/usenglish/isehelp/pp_db_xst_synthesis_options.htm ( 1 )
 
Project Statistics
PROPEXT_SynthMultStyle_virtex2=Block PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthOptEffort=High PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2012-11-10T23:16:05
PROP_intWbtProjectID=07482C70AD8BC6B64237A3D6743223A9 PROP_intWbtProjectIteration=12
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone=true PROP_xilxMapAllowLogicOpt=true
PROP_xilxMapCoverMode=Speed PROP_xilxMapPackRegInto=For Inputs and Outputs
PROP_xilxMapTimingDrivenPacking=true PROP_xilxPARplacerEffortLevel=High
PROP_xilxPARrouterEffortLevel=High PROP_xilxPostTrceRpt=Error Report
PROP_xilxSynthRegBalancing=Yes PROP_xstBusDelimiter={}
PROP_xstEquivRegRemoval=false PROP_xstOptimizeInsPrimtives=true
PROP_xstPackIORegister=Yes PROP_AutoTop=true
PROP_DevFamily=Spartan3 PROP_MapLogicOptimization=true
PROP_MapRegDuplication=On PROP_SynthMuxStyle=MUXCY
PROP_DevDevice=xc3s1000 PROP_DevFamilyPMName=spartan3
PROP_MapExtraEffort=Normal PROP_xilxPARextraEffortLevel=Normal
PROP_DevPackage=ft256 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-5 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=28
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_DCM=2 NGDBUILD_NUM_FD=2583 NGDBUILD_NUM_FDDRCPE=28
NGDBUILD_NUM_FDE=1993 NGDBUILD_NUM_FDR=172 NGDBUILD_NUM_FDRE=39 NGDBUILD_NUM_FDRS=3
NGDBUILD_NUM_FDS=42 NGDBUILD_NUM_FDSE=4 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=66
NGDBUILD_NUM_IBUFG=2 NGDBUILD_NUM_INV=361 NGDBUILD_NUM_IOBUF=17 NGDBUILD_NUM_LUT1=239
NGDBUILD_NUM_LUT2=1511 NGDBUILD_NUM_LUT2_D=4 NGDBUILD_NUM_LUT2_L=3 NGDBUILD_NUM_LUT3=1585
NGDBUILD_NUM_LUT3_D=15 NGDBUILD_NUM_LUT3_L=14 NGDBUILD_NUM_LUT4=1268 NGDBUILD_NUM_LUT4_D=74
NGDBUILD_NUM_LUT4_L=170 NGDBUILD_NUM_MULT18X18S=23 NGDBUILD_NUM_MUXCY=2640 NGDBUILD_NUM_MUXF5=231
NGDBUILD_NUM_MUXF6=32 NGDBUILD_NUM_OBUF=70 NGDBUILD_NUM_RAM16X1D=12 NGDBUILD_NUM_RAM16X1S=14
NGDBUILD_NUM_SRL16=51 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=2633
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_DCM=2 NGDBUILD_NUM_FD=2583 NGDBUILD_NUM_FDDRCPE=28
NGDBUILD_NUM_FDE=1993 NGDBUILD_NUM_FDR=172 NGDBUILD_NUM_FDRE=39 NGDBUILD_NUM_FDRS=3
NGDBUILD_NUM_FDS=42 NGDBUILD_NUM_FDSE=4 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=85
NGDBUILD_NUM_IBUFG=2 NGDBUILD_NUM_INV=361 NGDBUILD_NUM_LUT1=239 NGDBUILD_NUM_LUT2=1511
NGDBUILD_NUM_LUT2_D=4 NGDBUILD_NUM_LUT2_L=3 NGDBUILD_NUM_LUT3=1585 NGDBUILD_NUM_LUT3_D=15
NGDBUILD_NUM_LUT3_L=14 NGDBUILD_NUM_LUT4=1268 NGDBUILD_NUM_LUT4_D=74 NGDBUILD_NUM_LUT4_L=170
NGDBUILD_NUM_MULT18X18S=23 NGDBUILD_NUM_MUXCY=2640 NGDBUILD_NUM_MUXF5=231 NGDBUILD_NUM_MUXF6=32
NGDBUILD_NUM_OBUF=70 NGDBUILD_NUM_OBUFT=17 NGDBUILD_NUM_PULLDOWN=60 NGDBUILD_NUM_PULLUP=4
NGDBUILD_NUM_RAM16X1S=14 NGDBUILD_NUM_RAMB16_S18_S18=2 NGDBUILD_NUM_RAMB16_S4_S4=16 NGDBUILD_NUM_SRLC16E=51
NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=2633
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s1000-5-ft256 -top=<design_top> -opt_mode=Speed -opt_level=2
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter={} -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Block -iobuf=YES -max_fanout=500 -bufg=8
-register_duplication=YES -register_balancing=Yes -move_first_stage=YES -move_last_stage=YES
-optimize_primitives=YES -use_clock_enable=Yes -use_sync_set=Yes -use_sync_reset=Yes
-iob=True -equivalent_register_removal=NO -slice_utilization_ratio_maxmargin=5