/*
 This is the local (on-chip) bus acknowledgment and data mux. Uses
 per module clock enables to route module acks and readback data

 Copyright (c) 2006 Dimtel, Inc., All Rights Reserved

 $Id: busmux.v,v 1.2 2009/08/29 19:54:11 dim Exp $
 $Date: 2009/08/29 19:54:11 $
 $Author: dim $
 $Revision: 1.2 $
 $Log: busmux.v,v $
 Revision 1.2  2009/08/29 19:54:11  dim
 Added timescale

 Revision 1.1.1.1  2009/02/05 07:20:51  dim
 Initial import

 Revision 1.2  2006/11/29 22:59:21  dim
 Data acquisition support added, 16-tap FIR, MAX1202, AD8842, EP195

 Revision 1.1.1.1  2006/11/27 07:48:46  dim
 Initial import

*/

`timescale 1ns/100ps

`include "bus_width.h"

module busmux32(
 input [31:0] cebus,	// Clock enables for individual modules
 input [31:0] ackbus,	// Acks for individual modules
 input        strobe,	// Bus strobe for voidack case
 output reg   ack,	// Muxed ack to bus master
 input [`IFACE-1:0] d31,
 input [`IFACE-1:0] d30,
 input [`IFACE-1:0] d29,
 input [`IFACE-1:0] d28,
 input [`IFACE-1:0] d27,
 input [`IFACE-1:0] d26,
 input [`IFACE-1:0] d25,
 input [`IFACE-1:0] d24,
 input [`IFACE-1:0] d23,
 input [`IFACE-1:0] d22,
 input [`IFACE-1:0] d21,
 input [`IFACE-1:0] d20,
 input [`IFACE-1:0] d19,
 input [`IFACE-1:0] d18,
 input [`IFACE-1:0] d17,
 input [`IFACE-1:0] d16,
 input [`IFACE-1:0] d15,
 input [`IFACE-1:0] d14,
 input [`IFACE-1:0] d13,
 input [`IFACE-1:0] d12,
 input [`IFACE-1:0] d11,
 input [`IFACE-1:0] d10,
 input [`IFACE-1:0] d9,
 input [`IFACE-1:0] d8,
 input [`IFACE-1:0] d7,
 input [`IFACE-1:0] d6,
 input [`IFACE-1:0] d5,
 input [`IFACE-1:0] d4,
 input [`IFACE-1:0] d3,
 input [`IFACE-1:0] d2,
 input [`IFACE-1:0] d1,
 input [`IFACE-1:0] d0,
 output reg [`IFACE-1:0] data
);

  always @(cebus or ackbus or d31 or d30 or d29 or d28 or d27 or d26 or d25
        or d24 or d23 or d22 or d21 or d20 or d19 or d18 or d17 or d16 or
        d15 or d14 or d13 or d12 or d11 or d10 or d9 or d8 or d7 or d6 or d5
        or d4 or d3 or d2 or d1 or d0 or strobe)
    case (cebus)
      32'h00000001: begin ack  = ackbus[0];  data = d0; end
      32'h00000002: begin ack  = ackbus[1];  data = d1; end
      32'h00000004: begin ack  = ackbus[2];  data = d2; end
      32'h00000008: begin ack  = ackbus[3];  data = d3; end
      32'h00000010: begin ack  = ackbus[4];  data = d4; end
      32'h00000020: begin ack  = ackbus[5];  data = d5; end
      32'h00000040: begin ack  = ackbus[6];  data = d6; end
      32'h00000080: begin ack  = ackbus[7];  data = d7; end
      32'h00000100: begin ack  = ackbus[8];  data = d8; end
      32'h00000200: begin ack  = ackbus[9];  data = d9; end
      32'h00000400: begin ack  = ackbus[10]; data = d10; end
      32'h00000800: begin ack  = ackbus[11]; data = d11; end
      32'h00001000: begin ack  = ackbus[12]; data = d12; end
      32'h00002000: begin ack  = ackbus[13]; data = d13; end
      32'h00004000: begin ack  = ackbus[14]; data = d14; end
      32'h00008000: begin ack  = ackbus[15]; data = d15; end
      32'h00010000: begin ack  = ackbus[16]; data = d16; end
      32'h00020000: begin ack  = ackbus[17]; data = d17; end
      32'h00040000: begin ack  = ackbus[18]; data = d18; end
      32'h00080000: begin ack  = ackbus[19]; data = d19; end
      32'h00100000: begin ack  = ackbus[20]; data = d20; end
      32'h00200000: begin ack  = ackbus[21]; data = d21; end
      32'h00400000: begin ack  = ackbus[22]; data = d22; end
      32'h00800000: begin ack  = ackbus[23]; data = d23; end
      32'h01000000: begin ack  = ackbus[24]; data = d24; end
      32'h02000000: begin ack  = ackbus[25]; data = d25; end
      32'h04000000: begin ack  = ackbus[26]; data = d26; end
      32'h08000000: begin ack  = ackbus[27]; data = d27; end
      32'h10000000: begin ack  = ackbus[28]; data = d28; end
      32'h20000000: begin ack  = ackbus[29]; data = d29; end
      32'h40000000: begin ack  = ackbus[30]; data = d30; end
      32'h80000000: begin ack  = ackbus[31]; data = d31; end
      32'h00000000: begin ack  = strobe; data = 32'hdeadbeef; end
      default: begin
        ack  = 1'b0; // Multiple CE's asserted, hangs the bus
        data = 32'h0bad0bad;
      end
    endcase

endmodule // busmux

module busmux16(
 input [15:0] cebus,	// Clock enables for individual modules
 input [15:0] ackbus,	// Acks for individual modules
 input        strobe,	// Bus strobe for voidack case
 output reg   ack,	// Muxed ack to bus master
 input [`IFACE-1:0] d15,
 input [`IFACE-1:0] d14,
 input [`IFACE-1:0] d13,
 input [`IFACE-1:0] d12,
 input [`IFACE-1:0] d11,
 input [`IFACE-1:0] d10,
 input [`IFACE-1:0] d9,
 input [`IFACE-1:0] d8,
 input [`IFACE-1:0] d7,
 input [`IFACE-1:0] d6,
 input [`IFACE-1:0] d5,
 input [`IFACE-1:0] d4,
 input [`IFACE-1:0] d3,
 input [`IFACE-1:0] d2,
 input [`IFACE-1:0] d1,
 input [`IFACE-1:0] d0,
 output reg [`IFACE-1:0] data
);

  always @(cebus or ackbus or d15 or d14 or d13 or d12 or d11 or d10 or d9
        or d8 or d7 or d6 or d5 or d4 or d3 or d2 or d1 or d0 or strobe)
    case (cebus)
      16'h0001: begin
        ack  = ackbus[0];
        data = d0;
      end
      16'h0002: begin
        ack  = ackbus[1];
        data = d1;
      end
      16'h0004: begin
        ack  = ackbus[2];
        data = d2;
      end
      16'h0008: begin
        ack  = ackbus[3];
        data = d3;
      end
      16'h0010: begin
        ack  = ackbus[4];
        data = d4;
      end
      16'h0020: begin
        ack  = ackbus[5];
        data = d5;
      end
      16'h0040: begin
        ack  = ackbus[6];
        data = d6;
      end
      16'h0080: begin
        ack  = ackbus[7];
        data = d7;
      end
      16'h0100: begin
        ack  = ackbus[8];
        data = d8;
      end
      16'h0200: begin
        ack  = ackbus[9];
        data = d9;
      end
      16'h0400: begin
        ack  = ackbus[10];
        data = d10;
      end
      16'h0800: begin
        ack  = ackbus[11];
        data = d11;
      end
      16'h1000: begin
        ack  = ackbus[12];
        data = d12;
      end
      16'h2000: begin
        ack  = ackbus[13];
        data = d13;
      end
      16'h4000: begin
        ack  = ackbus[14];
        data = d14;
      end
      16'h8000: begin
        ack  = ackbus[15];
        data = d15;
      end
      16'h0000: begin
        ack  = strobe;
        data = 32'hdeadbeef;
      end
      default: begin
        ack  = 1'b0;
        data = 32'h0bad0bad;
      end
    endcase

endmodule // busmux
