/*
 This module detects a rising edge on "in" and produces a one-cycle
 output pulse.

 Copyright (c) 2006 Dimtel, Inc., All Rights Reserved

 $Id: detedge.v,v 1.2 2012/09/25 20:03:51 dim Exp $
 $Date: 2012/09/25 20:03:51 $
 $Author: dim $
 $Revision: 1.2 $
 $Log: detedge.v,v $
 Revision 1.2  2012/09/25 20:03:51  dim
 Added timescale

 Revision 1.1.1.1  2009/02/05 07:20:51  dim
 Initial import

 Revision 1.1.1.1  2006/11/27 07:48:46  dim
 Initial import

*/

`timescale 1ns/100ps

module detedge(
  input		clk,
  input 	in,
  output	out
);
  reg bit = 1'b0;
  
  always @(posedge clk) bit <= in;
  
  assign out = in & ~bit;
endmodule // detedge
