/*
 DCM reset generator. A 16-bit counter starts after the input
 falling edge (1.3 ms). Every falling edge afterwards restarts the counting.
 When reaching terminal count the reset pulse is generated.

 Copyright (c) 2006 Dimtel, Inc., All Rights Reserved

 $Id: dcm_rst.v,v 1.1.1.1 2009/02/05 07:20:51 dim Exp $
 $Date: 2009/02/05 07:20:51 $
 $Author: dim $
 $Revision: 1.1.1.1 $
 $Log: dcm_rst.v,v $
 Revision 1.1.1.1  2009/02/05 07:20:51  dim
 Initial import

 Revision 1.1  2007/02/09 00:35:50  dim
 Final 16-bit version of the gateware


*/

module dcm_rst(
  input		clk,
  input		clkmiss,
  output 	rst
);

  reg [11:0] counter = 12'b0;
  reg [11:0] rst_cnt = 12'b0;
  reg [2:0] clkmiss_resync;
  wire fall, rst_int;
  
  assign fall = clkmiss_resync[1] & ~clkmiss_resync[2];
  assign rst_int = (counter == 12'hfff);
  always @(posedge clk) begin
    clkmiss_resync <= {clkmiss_resync[1:0], clkmiss};
    counter <= (fall) ? 12'b1 : (counter != 12'b0) ? counter + 12'b1 : 12'b0;
    rst_cnt <= (rst_int) ? 12'b1 : (rst_cnt != 12'b0) ? rst_cnt + 12'b1 : 12'b0;
  end
  assign rst = (rst_cnt != 12'b0);

endmodule // dcm_rst
