/*
 Status readback register, resets on read

 $Id: sreg.v,v 1.1.1.1 2009/02/05 07:20:51 dim Exp $
 $Date: 2009/02/05 07:20:51 $
 $Author: dim $
 $Revision: 1.1.1.1 $
 $Log: sreg.v,v $
 Revision 1.1.1.1  2009/02/05 07:20:51  dim
 Initial import

 Revision 1.2  2007/03/14 08:37:48  dim
 Gateware revision 1.01: first release of full iGp functionality

 Revision 1.1.1.1  2006/11/27 07:48:46  dim
 Initial import

*/

`include "bus_width.h"

module sreg(clk, strobe, ce, rd, ack, dout, bits);
  input clk, strobe, ce, rd;
  input [`IFACE-1:0] bits;

  output ack;
  output [`IFACE-1:0] dout;

  wire clk, strobe, ce, rd;
  wire [`IFACE-1:0] bits;

  reg ack = 1'b0;
  reg [`IFACE-1:0] dout = 32'h0000;

  reg [`IFACE-1:0] rsa = 32'h0000, rsb = 32'h0000, holder = 32'h0000;

  // Resync to lclk
  always @(posedge clk) begin
    rsa <= bits;
    rsb <= rsa;
    if (ce & strobe & ~ack & rd) begin
      dout <= holder;
      holder <= 32'h0000;
      ack <= 1'b1;
    end
    else
      holder <= holder | rsb;

    if (ack) ack <= 1'b0;
  end
endmodule // sreg
