/*
 FX2 firmware: main init code and event loop
 
 This firmware configures slave FIFO interface for the FPGA communications
 using usbio library and fx2.v local bus master module.
 
 Copyright (c) 2008 Dimtel, Inc., All Rights Reserved

 $Id: main.c,v 1.3 2013/09/05 03:22:42 dim Exp $
 $Date: 2013/09/05 03:22:42 $
 $Author: dim $
 $Revision: 1.3 $
 $Log: main.c,v $
 Revision 1.3  2013/09/05 03:22:42  dim
 Converted count from ushort to ucharto specify 4-byte blocks (128 max)

 Revision 1.2  2013/06/06 04:35:11  dim
 Added EP8 OUT to interface 0 for fast JTAG block loading

 Revision 1.1  2012/11/11 01:24:32  dim
 Moved from BxB, adapted to compile for both LLRF4 and IGP12

 Revision 1.1  2011/12/27 19:31:47  dim
 Updated to remove deprecated constructs (at, sfr, xdata, sbit)


*/

#include "common.h"
#include "fifo.h"
#include "fx2regs.h"
#include "interrupts.h"
#include "usb.h"
#include "hwdef.h"
#include "jtag.h"

extern volatile __bit SUDAV_service;

void main(void)
{
  /* Initialize clock output, interface mode, CPU clock, JTAG bits */
  basic_init();

  /* Set up endpoint FIFOs */
  fifo_init();
  
  fpga_reset();


  /* USB interrupts */
  setup_interrupts();

  /* Renumerate - we are ready to handle USB requests */
  renumerate();

  while (1)
  {
    if (SUDAV_service)
      usb_setup_handler();
    while ((EP8CS & bmEPEMPTY) == 0)
    {
      uchar count = (EP8BCL>>3) | (EP8BCH<<5);
      jtag_block_write_ep8(count);
    }
  }
}
