/*
 Clock detector module
 Samples DSP clock/16 by the local bus clock and looks for missing edges.

 $Id: clkdet.v,v 1.1.1.1 2009/02/05 07:20:51 dim Exp $
 $Date: 2009/02/05 07:20:51 $
 $Author: dim $
 $Revision: 1.1.1.1 $
 $Log: clkdet.v,v $
 Revision 1.1.1.1  2009/02/05 07:20:51  dim
 Initial import

 Revision 1.2  2007/03/14 08:37:48  dim
 Gateware revision 1.01: first release of full iGp functionality

 Revision 1.1.1.1  2006/11/27 07:48:46  dim
 Initial import

*/

module clkdet #(parameter div_bit=3) (clk, dspclk, clkmiss);
  input clk, dspclk;

  output clkmiss;

  reg [3:0] div = 4'h0;
  reg [8:0] r = 9'h0;

  // Clock divider
  always @(posedge dspclk)
    div <= div + 4'b1;

  // Metastability resync
  always @(posedge clk) r[0] <= div[div_bit];

  always @(posedge clk) r[1] <= r[0];
  always @(posedge clk) r[2] <= r[1];
  always @(posedge clk) r[3] <= r[2];
  always @(posedge clk) r[4] <= r[3];
  always @(posedge clk) r[5] <= r[4];
  always @(posedge clk) r[6] <= r[5];
  always @(posedge clk) r[7] <= r[6];
  always @(posedge clk) r[8] <= r[7];

  assign clkmiss = (r[8:1] == 8'hff) | (r[8:1] == 8'h00);
endmodule // clkdet
