/*
 FPGA register map and bit masks. Unfortunately this map is not used directly
 by the database files, so certain register and memory addresses are
 hardcoded in .db files.
 
 Copyright (c) 2008-2009 Dimtel, Inc., All Rights Reserved

 $Id: map.h,v 1.4 2012/11/11 05:48:57 dim Exp $
 $Date: 2012/11/11 05:48:57 $
 $Author: dim $
 $Revision: 1.4 $
 $Log: map.h,v $
 Revision 1.4  2012/11/11 05:48:57  dim
 Updates in 2009-2012 range

 Revision 1.3  2009/06/07 16:53:11  dim
 Added header


*/

#ifndef _MAP_H_
#define _MAP_H_

#define CSR_A_CTRL  			0x0
#define CTRL_B_ADC0 0
#define CTRL_M_ADC0 (1<<CTRL_B_ADC0)
#define CTRL_B_ADC1 1
#define CTRL_M_ADC1 (1<<CTRL_B_ADC1)
#define CTRL_B_ADC2 2
#define CTRL_M_ADC2 (1<<CTRL_B_ADC2)
#define CTRL_B_ADC3 3
#define CTRL_M_ADC3 (1<<CTRL_B_ADC3)
#define CTRL_B_DAC  4
#define CTRL_M_DAC  (1<<CTRL_B_DAC)
#define CTRL_B_DCMRST 5
#define CTRL_M_DCMRST (1<<CTRL_B_DCMRST)

#define CSR_A_TRIG  			0x1
#define CSR_A_PHDCM0			0x2
#define CSR_A_SCALAR			0x3
#define CSR_A_DDS0			0x4
#define DDS0_B_ADV		0
#define DDS0_V_ADV		0x1ffff
#define DDS0_M_ADV		(DDS0_V_ADV << DDS_B_ADV)
#define DDS0_B_SQUARE		17
#define DDS0_B_MN		20
#define DDS0_V_MN		0xfff
#define DDS0_M_MN		(DDS0_V_MN << DDS_B_MN)
#define CSR_A_DDS1			0x5
#define DDS1_B_REM		0
#define DDS1_V_REM		0xfff
#define DDS1_M_REM		(DDS1_V_REM << DDS1_B_REM)
#define DDS1_B_AMP		16
#define DDS1_V_AMP		0x3fff
#define DDS1_M_AMP		(DDS1_V_AMP << DDS1_B_AMP)
#define CSR_A_DDS2			0x6
#define DDS2_B_ROTI		0
#define DDS2_V_ROTI		0xffff
#define DDS2_M_ROTI		(DDS2_V_ROTI << DDS2_B_ROTI)
#define DDS2_B_ROTQ		16
#define DDS2_V_ROTQ		0xffff
#define DDS2_M_ROTQ		(DDS2_V_ROTQ << DDS2_B_ROTQ)
#define DDS_V_AMPFS		4970

#define AD5644_A_CH0			0x10
#define AD5644_A_CH1			0x11
#define AD5644_A_CH2			0x12
#define AD5644_A_CH3			0x13
#define AD5644_A_CH4			0x14
#define AD5644_A_CH5			0x15
#define AD5644_A_CH6			0x16
#define AD5644_A_CH7			0x17
#define AD5644_A_CH8			0x18
#define AD5644_A_CH9			0x19
#define AD5644_A_CH10			0x1a
#define AD5644_A_CH11			0x1b
#define AD5644_A_REF0			0x1c
#define AD5644_A_REF1			0x1d
#define AD5644_A_REF2			0x1e
#define AD5644_A_TEST			0x1f

#define CSR_A_ARM			0x20

#define IIR_COEFF_BITS			16
#define CSR_A_A10			0x100
#define CSR_A_A20			0x102
#define CSR_A_B00			0x104
#define CSR_A_B10			0x106
#define CSR_A_B20			0x108

#define CSR_A_STAT			0x200

#define CSR_A_AD9512			0x400
#define AD9512_LENGTH 0x5b
#define AD9512_A_SPICFG			0x0
#define AD9512_V_SPICFG			0x10
#define AD9512_A_BYPASS			0x34
#define AD9512_A_RAMP			0x35
#define AD9512_RAMP_B_IRAMP	0
#define AD9512_RAMP_B_CRAMP	3
#define AD9512_A_DELAY  		0x36
#define AD9512_DELAY_B_DELAY	1
#define AD9512_A_OUT0			0x3d
#define AD9512_OUT012_B_PD	1
#define AD9512_OUT012_B_LEVEL	2
#define AD9512_V_OUT012		0xb		/* Unused output power down */
#define AD9512_A_OUT1			0x3e
#define AD9512_A_OUT2			0x3f
#define AD9512_A_OUT3			0x40
#define AD9512_OUT34_B_PD	0
#define AD9512_OUT34_B_CURR	1
#define AD9512_OUT34_B_LOGIC	3
#define AD9512_OUT34_B_INV	4
#define AD9512_A_OUT4			0x41
#define AD9512_A_CLKSEL			0x45
#define AD9512_V_CLKSEL		2		/* Use CLK2, power down CLK1 */
#define AD9512_A_DIV0			0x4a
#define AD9512_A_DIV0			0x4a
#define AD9512_A_DIV1			0x4c
#define AD9512_A_DIV2			0x4e
#define AD9512_A_DIV3			0x50
#define AD9512_A_CFG3			0x51
#define AD9512_A_DIV4			0x52
#define AD9512_A_CFG4			0x53
#define AD9512_CFG_B_BYPASS	7
#define AD9512_V_DIV		0xff
#define AD9512_A_SYNC			0x58
#define AD9512_SYNC_B_SOFT	2
#define AD9512_A_UPD			0x5a

/* On-chip blockRAM starts at 0x10000. Total decoded space is 0x10000,
   however not all machines have all of the space fully used. */
#define BLOCKRAM	0x10000
#define BLOCKRAM_LENGTH	8192

/* Scalar readout registers */
#define SCALAR_A_BASE   0x18000
#define MCP3208_A_CH0	0x18010
#define MCP3208_A_CH1	0x18011
#define MCP3208_A_CH2	0x18012
#define MCP3208_A_CH3	0x18013
#define MCP3208_A_CH4	0x18014
#define MCP3208_A_CH5	0x18015
#define MCP3208_A_CH6	0x18016
#define MCP3208_A_CH7	0x18017
#define DS1822_A_ROM0	0x18018
#define DS1822_A_ROM1	0x18019
#define DS1822_A_TEMP	0x1801a
#define DS1822_A_STAT	0x1801b
#define FANMON_A_BASE	0x1801c
#define FANMON_LENGTH	2
#define FREQCNT_A_VAL	0x18020
#define SCALAR_LENGTH	(FREQCNT_A_VAL - SCALAR_A_BASE + 1)

/* Drive generator memory */
#define DRIVERAM        0x40000
#define DRIVERAM_LENGTH 0x400

#endif /* _MAP_H_ */
