/*
 Drive pattern generator for the DAC.

 Copyright (c) 2008 Dimtel, Inc., All Rights Reserved

 $Id: drv_arb.v,v 1.1.1.1 2009/06/02 20:26:02 dim Exp $
 $Date: 2009/06/02 20:26:02 $
 $Author: dim $
 $Revision: 1.1.1.1 $
 $Log: drv_arb.v,v $
 Revision 1.1.1.1  2009/06/02 20:26:02  dim
 Initial import


*/

`include "bus_width.h"

module drv_arb(
  input		clk, 
  input		strobe,
  input		ce,
  input		rd,
  output	ack,
  input [9:0]	addr,
  input [`IFACE-1:0] din,
  output [`IFACE-1:0] dout,
	
  // High-speed port clock and data
  input		dspclk,
  output [27:0]	dac_out
);
  
  reg [9:0] dac_addr = 10'b0;
  wire [31:0] mem_out;
  
  // Playback address counter - always on
  always @(posedge dspclk)
    dac_addr <= dac_addr + 10'b1;
        
  mem_play2 mem(.clk(clk), .strobe(strobe), .ce(ce), .rd(rd),
                .ack(ack), .addr(addr), .din(din), .dout(dout),
                     .clk2(dspclk), .addr2(dac_addr), .play(mem_out));
  
  assign dac_out = {mem_out[29:16], mem_out[13:0]};
endmodule /* drv_arb */
