/*
 DAC DDR output module, accepts 2's complement inputs

 Copyright (c) 2008 Dimtel, Inc., All Rights Reserved

 $Id: dac_ddr.v,v 1.1.1.1 2009/06/02 20:26:02 dim Exp $
 $Date: 2009/06/02 20:26:02 $
 $Author: dim $
 $Revision: 1.1.1.1 $
 $Log: dac_ddr.v,v $
 Revision 1.1.1.1  2009/06/02 20:26:02  dim
 Initial import


*/

module dac_ddr(
  input [27:0]	dac,
  input 	dac_clk,
  input		dac_clk180,
  output [13:0]	dacout
);

  generate
  genvar i;
  for (i = 0; i < 14; i = i + 1) begin: dac_
    if (i == 13)
      FDDRCPE ddr(.C0(dac_clk), .C1(dac_clk180), .D0(~dac[i]), .D1(~dac[i+14]),
                  .Q(dacout[i]),
                  .CE(1'b1), .PRE(1'b0), .CLR(1'b0));
    else
      FDDRCPE ddr(.C0(dac_clk), .C1(dac_clk180), .D0(dac[i]), .D1(dac[i+14]),
                  .Q(dacout[i]),
                  .CE(1'b1), .PRE(1'b0), .CLR(1'b0));
  end
  endgenerate

endmodule // dac_ddr
