/*
 Address decoder. Here all of the address mapping information is contained.

 Copyright (c) 2006 Dimtel, Inc., All Rights Reserved

 $Id: addrdec.v,v 1.3 2012/11/11 06:03:30 dim Exp $
 $Date: 2012/11/11 06:03:30 $
 $Author: dim $
 $Revision: 1.3 $
 $Log: addrdec.v,v $
 Revision 1.3  2012/11/11 06:03:30  dim
 Updates and fixes in 2009-2012 timeframe

 Revision 1.2  2009/06/02 23:00:36  dim
 Header cleanup

 Revision 1.1.1.1  2009/06/02 20:26:02  dim
 Initial import

*/

module addrdec(
  input [31:0] addr,
  output reg0ce,
  output dacq_ce,
  output block0ce,
  output block1ce,
  output ad9512ce,
  output stat_ce,
  output dcm0ce,
  output scalarce,
  output [4:0] ddsce,
  output arbce,
  output [3:0] rmsce,
  output IQce,
  output iirce,
  output ad5644ce,
  output mcp3208ce,
  output ds1822ce,
  output freq_ce,
  output fanmonce,
  output waitce
);
  // Register at 0x0
  assign reg0ce   = addr == 32'h0;
  
  // Data acquisition trigger at 0x1
  assign dacq_ce = addr == 32'h1;
  
  // DCM control register at 0x2
  assign dcm0ce  = addr == 32'h2;
  
  // Scalar data decimation register at 0x3
  assign scalarce = addr == 32'h3;
  
  // DDS register 0 at 0x4
  assign ddsce[0] = addr == 32'h4;
  
  // DDS register 1 at 0x5
  assign ddsce[1] = addr == 32'h5;
  
  // DDS register 2 at 0x6
  assign ddsce[2] = addr == 32'h6;
  
  // DDS register 3 at 0x7
  assign ddsce[3] = addr == 32'h7;
  
  // DDS register 4 at 0x8
  assign ddsce[4] = addr == 32'h8;

  // Status register at 0x200
  assign stat_ce = addr == 32'h200;
  
  // AD9512 registers memory-mapped at 0x400-0x47f
  assign ad9512ce = addr[31:7] == 25'h0_00_00_08;
  
  // Block ram at 0x10000-0x10fff (4k)
  assign block0ce = addr[31:12] == 20'h00_01_0;
  
  // Block ram at 0x11000-0x11fff (4k)
  assign block1ce = addr[31:12] == 20'h00_01_1;

  // RMS registers
  assign rmsce[0] = addr == 32'h18000;
  assign rmsce[1] = addr == 32'h18001;
  assign rmsce[2] = addr == 32'h18002;
  assign rmsce[3] = addr == 32'h18003;

  // DDC+CIC I/Q registers at 0x18008-0x1800f
  assign IQce = addr[31:3] == 29'h3001;
  
  // IIR registers at 0x100-0x107
  assign iirce    = addr[31:4] == 28'h10;
  
  // AD5644 registers at 0x10-0x1f
  assign ad5644ce = addr[31:4] == 28'h01;
  
  // MCP3208 registers at 0x18010-0x18017
  assign mcp3208ce = addr[31:3] == 29'h3002;
  
  // DS1822 registers at 0x18018-0x1801b
  assign ds1822ce  = addr[31:2] == 30'h6006;
  
  // Fan monitor at 0x1801c
  assign fanmonce  = addr[31:2] == 30'h6007;

  // Frequency counter at 0x18020
  assign freq_ce   = addr == 32'h18020;

  // ARB generator at 0x40000-0x4ffff
  assign arbce = addr[31:16] == 16'h4;

  // Wait-state tester at 0xc0000000-0xffffffff
  assign waitce   = addr[31:30] == 2'b11;
endmodule // addrdec
