iGp12 iGp12 is designed for the bunch-by-bunch feedback and diagnostics in lepton storage rings. Functionally iGp12 implements a baseband bunch-by-bunch processing channel configured to individually process all bunches in the ring. Signal for each bunch passes through a 32-tap FIR filter before being sent to the one-turn delay and, from there, to the high-speed DAC.

The main signal processing chain consists of a high-speed 12-bit ADC, an FPGA, and a high-speed DAC and is driven by the RF clock. In addition to performing real-time control computations, the FPGA interfaces to a number of on-board devices, such as high-speed data acquisition memory (SRAM), low-speed analog and digital I/O, as well as temperature and supply voltage monitors. In turn, the FPGA uses an internal USB connection to communicate to an embedded IOC computer housed in the same chassis. The IOC runs the Linux operating system and is connected to the overall control system via the Ethernet.

System control and diagnostics are performed via EPICS. All control and diagnostic features are accessible through the supplied EDM panels. Acquired diagnostic data can be exported to external tools for off-line analysis.

Consult the price list for iGp12 pricing. Contact Dimtel, Inc. for customization options, and delivery schedules.

Specifications | Technical user manuals | Revision history

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products/igp12.txt · Last modified: 2014/06/04 20:05 by dimtel
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