Adjustable in units of 3 samples, up to full memory length
Hold-off before recording
In units of 3 samples, 0 to 232-1
Recording downsampling
1 to 32
Monitoring and diagnostics
Parameter
Definition
Clock status
RF clock missing, DCM lock
Feedback channel status
FIR saturation
Acquisition state machine status
Trigger arming bit
Voltages
FPGA core supply, 3.3 V, 5 V, 12 V bulk
Temperatures
FPGA, ambient, two ECL devices, IOC CPU
Fan speeds
Chassis and IOC CPU
Analog inputs
8 slow ADC channels
Digital inputs
32 general-purpose inputs/outputs
Drive signal generator
Parameter
Definition
Output waveform
Sine, square, or DC
Amplitude
0 to DAC full scale
Bunch selectability
Bunch-by-bunch drive enable mask. Allows any subset of bunches to be driven
Frequency range, bunch-by-bunch mode
0–FRF/2
Frequency sweeping
Set by sweep span and period
Input power requirements
Parameter
Definition
Input voltage
115/230 VAC
Input current
2/1 A
Frequency
60/50 Hz
Voltage selection
Switch
Low voltage range
104–126 V
High voltage range
207–253 V
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products/specs/igp12.txt · Last modified: 2013/09/12 03:26 by dimtel