iGp Specifications
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Table of Contents

iGp Specifications

General

Parameter Definition
Sampling rate 100–550 MHz
FIR taps 16
Supported harmonic numbers 12–5120
Fiducial signal Falling edge trigger, NIM level
Minimum fiducial pulse width One RF period (TRF)
External trigger inputs 2 inputs, NIM level
Minimum trigger pulse width 2×TRF
Data acquisition memory 8 Msamples
Slow analog inputs 8 channels @ 12 bits
Slow analog outputs 7 channels @ 8 bits
Digital I/O 32 bidirectional signals, LVTTL

High-speed ADC & DAC

Parameter Definition
ADC inputs 2 (differential)
ADC input sensitivity 200 mV peak-to-peak (-10 dBm)
ADC resolution 8 bits
ADC input bandwidth 1.26 GHz
DAC outputs 2 (differential)
DAC output swing 500 mV peak-to-peak (-2 dBm)
DAC resolution 12 bits
DAC 10/90 rise time under 250 ps
DAC 90/10 fall time under 350 ps

FIR filter control

Parameter Definition
Coefficients 16 bit wide in Q15 format
Coefficient sets 2
Coefficient set select User controllable
Shift gain 0–7 (1–128 actual gain)
Downsampling 1–32

Control parameters

Parameter Definition
One-turn delay TRF per step, up to one revolution
ADC clock timing 0–TRF in 10 ps steps
DAC clock timing 0–TRF in 10 ps steps
Analog outputs 7 channels + high-speed DAC offset
High-speed DAC offset trim 1 channel
Digital outputs 32 general-purpose inputs/outputs

Data acquisition controls

Parameter Definition
Recording memory selection internal blockRAM or external SRAM
Measurement trigger internal (software) or external (hardware)
External trigger arming Single or after every beam data readout
Recorded growth length Adjustable in units of 4 samples, up to full memory length
Hold-off before recording In units of 4 samples, 0 to 232-1
Recording downsampling 1 to 32

Monitoring and diagnostics

Parameter Definition
Clock status RF clock missing, DCM lock
Feedback channel status FIR saturation
Acquisition state machine status Trigger arming bit
Voltages FPGA core supply, 3.3 V, 12 V bulk
Temperatures Fast ADC, FPGA, ambient, two ECL devices, IOC CPU
Fan speeds Chassis and IOC CPU
Analog inputs 8 slow ADC channels
Digital inputs 32 general-purpose inputs/outputs

Drive signal generator

Parameter Definition
Output waveform Sine, sawtooth, square, or arbitrary
Amplitude 0 to DAC full scale
Bunch selectability Bunch-by-bunch drive enable mask. Allows any subset of bunches to be driven
Frequency range, bunch-by-bunch mode 0–FRF/2
Frequency range, turn-by-turn mode 0–Frev/2

Input power requirements

Parameter Definition
Input voltage 115/230 VAC
Input current 2/1 A
Frequency 60/50 Hz
Voltage selection Switch
Low voltage range 104–126 V
High voltage range 207–253 V
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products/specs/igp.txt · Last modified: 2008/09/19 18:14 by dimtel
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